The features of the present invention may be used in the printing arts and, more particularly, in digital image processing and electrophotographic printing. In digital image processing there is a distinct advantage to being able to provide digital filtering in an efficient and low cost manner. With regard to efficiency, it is advantageous to design hardware implementations of digital filters that are efficient This efficiency has two factors, first a speed of processing factor, and second a hardware minimization factor. For example, improved processing efficiency or speed may be achieved by adding hardware, however, this may not be a practical solution when one has to consider the cost of the additional hardware. The second factor becomes increasingly important when implementing the device as an application specific integrated circuit (ASIC), where the addition of hardware elements may result in the need for a larger die package. Accordingly, the present invention provides a two-dimensional digital filter that is efficient with respect to processing speed and hardware implementation, as well.
Signal processing devices usually require filters, especially two-dimensional filters to process data in numerous ways. Well known electrophotographic systems, for example, the Xerox.RTM. Docutech Production Publisher.RTM., usually employ digital hardware and application specific integrated circuit (ASIC) devices specifically designed to provide digital filtering capabilities. Generally, this type of system would employ hardware, software, or a combination of both to implement the digital filtering capabilities required. Various approaches have been devised for the implementation of digital filtering techniques, of which the following disclosures appear to be relevant:
U.S. Pat. No. 4,766,561 PA1 Patentee: Thompson et al. PA1 Issued: Aug. 23, 1988 PA1 U.S. Pat. No. 4,777,612 PA1 Patentee Tomimitsu PA1 Issued: Oct. 11, 1988 PA1 U.S. Pat. No. 4,82 1,223 PA1 Patentee: David PA1 Issued: Apr. 11, 1989
The relevant portions of the foregoing patents may be briefly summarized as follows:
U.S. Pat. No. 4,766,561 to Thompson et al. discloses a circuit for performing a plurality of finite impulse response filtering functions. The circuit comprises a plurality of filters, each implementing a predetermined digital filter algorithm. A storage circuit stores coefficients and data operands utilized in implementing the predetermined algorithms. An arithmetic unit is coupled to the storage circuit for performing predetermined arithmetic operations with selected coefficient and data operands, and a sequencing control device sequentially selects operands from the storage circuit for input to the arithmetic unit.
U.S. Pat. No. 4,777,612 to Tomimitsu discloses a digital signal processing apparatus for providing high-speed digital filtering. The apparatus includes at least two digital filters in parallel and a multiplexer for alternatively outputting the outputs of the filters.
U.S. Pat. No. 4,821,223 to David describes a two-dimensional finite impulse response filter having a plurality of filter portions of substantially identical construction arranged in a parallel configuration A demultiplexer separates an input data signal comprising consecutive digital words and supplies each digital word in sequence to a separate filter portion. Subsequently, a multiplexer coupled to the outputs of the filter portions selectively outputs the filtered data from each filter portion in a sequence corresponding to the order of separation of the input data, thereby resulting in a filtered version of the original input data
The present invention seeks to overcome the limitations of the related references by providing a plurality of one-dimensional (1-D) transform units that may be selectively combined with an additional one-dimensional transform unit to produce a plurality of distinct two-dimensional (2-D) filters, any one of which is selectable on a pixel by pixel basis. Moreover, the present system has the added advantage of providing these two-dimensional finite impulse response filters without employing multiple, identically constructed two-dimensional filters arranged in a parallel fashion, thereby substantially reducing the complexity and cost of the filter hardware.
In accordance with one aspect of the present invention, there is provided an apparatus for implementing a plurality of two-dimensional digital filters having a plurality of first stage filters operating in a first dimension in combination with a single second stage filter, operating in a second dimension, the filter operating in the second dimension being suitable for receiving output from one of the filters operating in the first dimension. A controller, operating in conjunction with the filters is utilized for controlling the operation of all filters, as well as selection of the input source for the second dimension filter.
Pursuant to another aspect of the present invention, there is provided an apparatus for implementing the plurality of two-dimensional digital filters by separating the transformations carried out by the filters into separate elements, thereby reducing the complexity of the hardware needed to implement the filters.
Pursuant to another aspect of the present invention, there is provided a method for selectively filtering a single digital data element in a two-dimensional filter by first applying a selected one-dimensional transformation, said transformation being selected from a plurality of possible transformations. Next, storing the context associated with the single data element until the context is passed to the second one-dimensional transform, to produce the two-dimensional filtered output.